The present invention relates to a memory device. More particularly, the present invention relates to a semiconductor device and a method for fabricating the same having a stepped recess channel region including vertical silicon-on-insulator (SOI) channel structures.
When a channel length of a cell transistor is decreased, the ion concentration of a cell channel region is generally increased in order to maintain the threshold voltage of the cell transistor. An electric field in source/drain regions of the cell transistor is enhanced to increase leakage current. This results in degradation of the refresh characteristics of a dynamic random access memory (DRAM) structure. Therefore, there is a need for semiconductor devices in which the refresh characteristics are improved.
FIG. 1 is a simplified layout of a semiconductor device, wherein reference numerals 1 and 3 denote an active region, which is defined by a device isolation structure 30, and a gate region, respectively.
FIGS. 2a through 2c are simplified cross-sectional views illustrating a method for fabricating a semiconductor device, wherein FIGS. 2a through 2c are cross-sectional views taken along the line I-I′ of FIG. 1.
Referring to FIG. 2a, a semiconductor substrate 10 having a pad insulating film (not shown) is etched using a device isolation mask (not shown) to form a trench (not shown) defining a Fin-type active region 20. An insulating film for device isolation (not shown) is formed to fill the trench. The insulating film for device isolation is polished until the pad insulating film is exposed to form a device isolation structure 30. The pad insulating film is removed to expose the top surface of the Fin-type active region 20.
Referring to FIG. 2b, a predetermined thickness of the device isolation structure 30 is etched using a recess gate mask (not shown) defining a gate region 3 shown in FIG. 1 to protrude an upper part of the Fin-type active region 20 over the device isolation structure 30.
Referring to FIG. 2c, a gate insulating film 60 is formed over the protruded Fin-type active region 20. A gate structure 90 is formed over the gate insulating film 60 of the gate region 3 shown in FIG. 1 to fill the protruded Fin-type active region 20, wherein the gate structure 90 comprises a stacked structure of a gate electrode 70 and a gate hard mask layer pattern 80.
FIG. 3 is a simplified cross-sectional view illustrating a semiconductor device. Referring to FIG. 3, if a voltage above the threshold voltage is applied to the gate, an inversion layer IL and a depletion region DR are formed in a semiconductor substrate 10 under the gate insulating film 60.
According to the above method for fabricating a semiconductor device, it is difficult to secure On/Off characteristics of the cell transistor due to shrinkage of its channel length. Since the channel area of the device is limited, it is also difficult to obtain substantial driving current. Even through the Fin FET structure of the cell transistor (trigate) has been proposed in order to secure the channel area of the device, there are problems of lowering its threshold voltage, degrading its refresh characteristics, and increasing the degree of process complexity such as the process of etching the device isolation structure.